1. Technical Field of the Invention
This invention relates generally to signal processing and more particularly to logic gates.
2. Description of Related Art
Digital logic circuits such as AND gates, NAND gates, NOR gates, OR gates, exclusive OR gates, latches, inverters, flip-flops, et cetera are known to be used in a wide variety of electronic devices. For instance, digital logic circuits are used in all types of computers (e.g., laptops, personal computers, personal digital assistants, et cetera), entertainment equipment (e.g., receivers, televisions, et cetera), and wireless communication devices (e.g., cellular telephones, radios, wireless local area network devices, et cetera).
Typically, digital logic circuits are part of a larger circuit, which is fabricated on an integrated circuit. For example, a local oscillator within a radio frequency (RF) transmitter and/or receiver includes a plurality of flip-flops and logic gates in its divider feedback circuit to provide adjustable divider values. As is known, by adjusting the divider value in a local oscillator, the resulting local oscillation can be adjusted to desired values.
Within the feedback divider circuit, the logic gates are included to achieve divider values different than powers of 2. Issues arise with the use of traditional logic gates in applications that push the operating limits of an integrated circuit process. For example, for a multi-gigahertz frequency range of operation, traditional logic gates create a bottleneck for the local oscillator due to the time it takes for each logic gate to complete its function.
Another related issue results as supply voltages decrease for newer integrated circuit fabrication processes (e.g., CMOS, gallium arsenide, silicon germanium, et cetera). As the supply voltage decreases, the available voltage to enable stacked transistors within the logic gates decreases. As such, the transistors have slower rise and fall times than if more voltage were available. Accordingly, it takes longer for the logic gate to complete its function due to the slower rise and fall times.
One obvious solution for increasing the rise and fall times of logic gates is to increase the supply voltage. However, by increasing the supply voltage, power consumption increases, and, in many ways, defeats the benefit of newer integrated circuit fabrication processes.
Further, in high performance applications, such as a radio frequency integrated circuit, differential signaling is used to improve noise immunity. Accordingly, the logic gates within the divider circuit of the local oscillator are differential circuits. As is known, an AND function and an OR function are achieved by the same combination of stack transistors by switching the plurality of the inputs. The number of transistors in each stack is dependent on the number of inputs. For example, a 2 input AND gate or OR gate function has 2 sets of 2 transistor stacked on a current source, a 3 input AND gate or OR gate function has 2 sets of 3 transistor stacks, et cetera. As such, differential logic gates suffer from the above-mentioned issues as well.
Therefore, a need exists for a high-speed differential logic gate that operates effectively in the multi-gigahertz range and is power consumption efficient.